18 nov 2007
- 12:5512:55 18 nov 2007 difs. hist. +288 N Programación en VHDL/Ejemplos/Multiplexor Página nueva: library IEEE; use IEEE.STD_LOGIC_1164.all; entity MUX is :port (a, b ,sel: in bit; f : out bit); end MUX; architecture rtl of MUX is begin :--signal sel, a, b : std_logic; :process ...